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Features
* High Performance, Low Power AVR(R)32 UC 32-Bit Microcontroller
- Compact Single-cycle RISC Instruction Set Including DSP Instruction Set - Read-Modify-Write Instructions and Atomic Bit Manipulation - Performing 1.49 DMIPS / MHz Up to 91 DMIPS Running at 66 MHz from Flash (1 Wait-State) Up to 49 DMIPS Running at 33MHz from Flash (0 Wait-State) - Memory Protection Unit Multi-hierarchy Bus System - High-Performance Data Transfers on Separate Buses for Increased Performance - 15 Peripheral DMA Channels Improves Speed for Peripheral Communication Internal High-Speed Flash - 512K Bytes, 256K Bytes, 128K Bytes Versions - Single Cycle Access up to 33 MHz - Prefetch Buffer Optimizing Instruction Execution at Maximum Speed - 4ms Page Programming Time and 8ms Full-Chip Erase Time - 100,000 Write Cycles, 15-year Data Retention Capability - Flash Security Locks and User Defined Configuration Area Internal High-Speed SRAM, Single-Cycle Access at Full Speed - 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash) External Memory Interface on AT32UC3A0 Derivatives - SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses) Interrupt Controller - Autovectored Low Latency Interrupt Service with Programmable Priority System Functions - Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator - Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL) allowing Independant CPU Frequency from USB Frequency - Watchdog Timer, Real-Time Clock Timer Universal Serial Bus (USB) - Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed - Flexible End-Point Configuration and Management with Dedicated DMA Channels - On-chip Transceivers Including Pull-Ups Ethernet MAC 10/100 Mbps interface - 802.3 Ethernet Media Access Controller - Supports Media Independent Interface (MII) and Reduced MII (RMII) One Three-Channel 16-bit Timer/Counter (TC) - Three External Clock Inputs, PWM, Capture and Various Counting Capabilities One 7-Channel 16-bit Pulse Width Modulation Controller (PWM) Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART) - Independant Baudrate Generator, Support for SPI, IrDA and ISO7816 interfaces - Support for Hardware Handshaking, RS485 Interfaces and Modem Line Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals One Synchronous Serial Protocol Controller - Supports I2S and Generic Frame-Based Protocols One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible One 8-channel 10-bit Analog-To-Digital Converter 16-bit Stereo Audio Bitstream - Sample Rate Up to 50 KHz
*
*
AVR(R)32 32-Bit Microcontroller AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128 Preliminary Summary
* * * *
*
*
* * *
* * * * *
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* On-Chip Debug System (JTAG interface)
- Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
* 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins) * 5V Input Tolerant I/Os * Single 3.3V Power Supply or Dual 1.8V-3.3V Power Supply
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1. Description
The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance. The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher computation capabilities are achievable using a rich set of DSP instructions. The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access. For applications requiring additional memory, an external memory interface is provided on AT32UC3A0 derivatives. The Peripheral Direct Memory Access controller (PDCA) enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU. The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external oscillator sources, a Real-Time Clock and its associated timer keeps track of the time. The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. The PWM modules provides seven independent channels with many configuration options including polarity, edge alignment and waveform non overlap control. One PWM channel can trigger ADC conversions for more accurate close loop control implementations. The AT32UC3A also features many communication interfaces for communication intensive applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like flexible Synchronous Serial Controller, USB and Ethernet MAC are available. The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S. The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device like a USB Flash disk or a USB printer to be directly connected to the processor. The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module provides on-chip solutions for network-connected devices. AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive real-time trace, full-speed read/write memory access in addition to basic runtime control.
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2. Configuration Summary
The table below lists all AT32UC3A memory and package configurations:
Device AT32UC3A0512 AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128
Flash 512 Kbytes 256 Kbytes 128 Kbytes 512 Kbytes 256 Kbytes 128 Kbytes
SRAM 64 Kbytes 64 Kbytes 32 Kbytes 64 Kbytes 64 Kbytes 32 Kbytes
Ext. Bus Interface yes yes yes no no no
Ethernet MAC yes yes yes yes yes yes
Package 144 lead LQFP 144 lead LQFP 144 lead LQFP 100 lead TQFP 100 lead TQFP 100 lead TQFP
3. Abbreviations
* GCLK: Power Manager Generic Clock * GPIO: General Purpose Input/Output * HSB: High Speed Bus * MPU: Memory Protection Unit * OCD: On Chip Debug * PB: Peripheral Bus * PDCA: Peripheral Direct Memory Access Controller (PDC) version A * USBB: USB On-The-GO Controller version B
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4. Blockdiagram
Figure 4-1. Blockdiagram
TC K TD O TD I TM S
M C KO M D O [5..0] M SEO [1..0] EVTI_N EVTO _N VBU S D+ DID VBOF
NEXUS CLASS 2+ OCD
UC CPU
M EM O R Y PR O TEC TIO N U N IT
MEMORY INTERFACE
JTAG INTERFACE
LOC AL BU S IN TER FAC E
FAST G PIO
INSTR INTERFACE
PBB
DATA INTERFAC E
64 KB SR AM
FLASH CONTROLLER
USB INTERFACE DM A
S M M
M
M
M
S S
512 KB FLASH
S ETHERNET M AC
PB
GENERAL PURPOSE IOs
MDC, TXD [3..0], TX _C LK, TX_EN , TX_ER , SPEED M D IO
S
C O N FIG U R ATIO N HS B
S
R EG ISTERS BU S
M
EXTERNAL BUS INTERFACE (SDRAM & STATIC MEMORY CONTROLLER)
C O L, C R S, R XD [3..0], R X_C LK, R X_D V, RX_ER
DM A
HIG H SPEED BUS M ATRIX
D ATA[15..0] ADD R [23..0] N C S[3..0] NRD N W AIT N W E0 N W E1 N W E3 R AS C AS SD A10 SD C K SD C KE SD C S 0 SD W E
H SB
HSB-PB BRIDG E B
HSB-PB BRIDG E A
PB PBA
PERIPHER AL DM A C ON TR O LLER
INTERR UPT CO NTRO LLER
EXTIN T[7..0] KPS[7..0] N M I_N
EXTERNAL INTERRUPT C O NTRO LLER
USART1
GENERAL PURPOSE IOs
PA PB PC PX
R XD TXD CLK R TS, C TS D SR , D TR, D C D, R I R XD TXD CLK R TS, C TS
PDC
PA PB PC PX
R EAL TIM E C O UNTER
USART0 USART2 USART3
PDC
W ATC HDO G TIM ER 115 kHz RC O SC
XIN 32 XOU T32 XIN 0 XOU T0 XIN 1 XOU T1
SERIAL PER IPHERAL INTERFACE 0/1 SYN CHRO NO US SERIAL CO NTRO LLER
SC K M ISO , M OSI N PC S0 N PC S[3..1]
TX_CLO CK, TX _FRAM E_SYNC TX_DATA RX_CLO CK, RX_FRAM E_SYNC RX_DATA
PO W ER M ANAG ER CLO C K G ENERATO R CLO C K CO NTRO LLER SLEEP CO NTRO LLER RESET CO NTRO LLER
32 KHz O SC O SC 0 O SC 1 PLL0 PLL1
PDC
PDC
TW O -W IRE INTERFACE
PDC
SC L SD A
PULSE W IDTH M O DULATIO N CO NTRO LLER ANALO G TO DIG ITAL CO NVERTER AUDIO BITSTR EAM DAC
PDC
PW M [6..0]
PDC
RESET_N
GC LK [3..0]
AD [7..0] AD VR EF
PDC
A[2..0] B[2..0] C LK[2..0]
TIM ER /CO UN TER
D ATA[1..0] D ATAN [1..0]
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4.1
4.1.1
Processor and architecture
AVR32 UC CPU * 32-bit load/store AVR32A RISC architecture.
15 general-purpose 32-bit registers. 32-bit Stack Pointer, Program Counter and Link Register reside in register file. Fully orthogonal instruction set. Privileged and unprivileged modes enabling efficient and secure Operating Systems. Innovative instruction set together with variable instruction length ensuring industry leading code density. - DSP extention with saturating arithmetic, and a wide variety of multiply instructions. * 3 stage pipeline allows one instruction per clock cycle for most instructions. - Byte, half-word, word and double word memory access. - Multiple interrupt priority levels. * MPU allows for operating systems with memory protection. - - - - -
4.1.2
Debug and Test system * IEEE1149.1 compliant JTAG and boundary scan * Direct memory access and programming capabilities through JTAG interface * Extensive On-Chip Debug features in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+ * * * *
- Low-cost NanoTrace supported. Auxiliary port for high-speed trace information Hardware support for 6 Program and 2 data breakpoints Unlimited number of software breakpoints supported Advanced Program, Data, Ownership, and Watchpoint trace supported
4.1.3
Peripheral DMA Controller * Transfers from/to peripheral to/from any memory space without intervention of the processor. * Next Pointer Support, forbids strong real-time constraints on buffer management. * Fifteen channels
- - - - - Two for each USART Two for each Serial Synchronous Controller Two for each Serial Peripheral Interface One for each ADC Two for each TWI Interface
4.1.4
Bus system * High Speed Bus (HSB) matrix with 6 Masters and 6 Slaves handled
- Handles Requests from the CPU Data Fetch, CPU Instruction Fetch, PDCA, USBB, Ethernet Controller, CPU SAB, and to internal Flash, internal SRAM, Peripheral Bus A, Peripheral Bus B, EBI. - Round-Robin Arbitration (three modes supported: no default master, last accessed default
master, fixed default master)
- Burst Breaking with Slot Cycle Limit - One Address Decoder Provided per Master
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* Peripheral Bus A able to run on at divided bus speeds compared to the High Speed Bus
Figure 4-1 gives an overview of the bus system. All modules connected to the same bus use the same clock, but the clock to each module can be individually shut off by the Power Manager. The figure identifies the number of master and slave interfaces of each module connected to the High Speed Bus, and which DMA controller is connected to which peripheral.
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5. Signals Description
The following table gives details on the signal name classified by peripheral The signals are multiplexed with GPIO pins as described in "Peripheral Multiplexing on I/O lines" on page 30.
Table 5-1.
Signal Name
Signal Description List
Function Power Type Active Level Comments
VDDPLL
Power supply for PLL
Power Input Power Input Power Input Power Input Power Input Power Output Ground Ground Clocks, Oscillators, and PLL's
1.65V to 1.95 V
VDDCORE
Core Power Supply
1.65V to 1.95 V
VDDIO
I/O Power Supply
3.0V to 3.6V
VDDANA
Analog Power Supply
3.0V to 3.6V
VDDIN
Voltage Regulator Input Supply
3.0V to 3.6V
VDDOUT GNDANA GND
Voltage Regulator Output Analog Ground Ground
1.65V to 1.95 V
XIN0, XIN1, XIN32 XOUT0, XOUT1, XOUT32
Crystal 0, 1, 32 Input Crystal 0, 1, 32 Output JTAG
Analog Analog
TCK TDI TDO TMS
Test Clock Test Data In Test Data Out Test Mode Select
Input Input Output Input Auxiliary Port - AUX
MCKO MDO0 - MDO5
Trace Data Output Clock Trace Data Output
Output Output
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Table 5-1.
Signal Name MSEO0 - MSEO1 EVTI_N EVTO_N
Signal Description List
Function Trace Frame Control Event In Event Out Type Output Output Output Power Manager - PM Low Low Active Level Comments
GCLK0 - GCLK3 RESET_N
Generic Clock Pins Reset Pin
Output Input Real Time Counter - RTC Low
RTC_CLOCK
RTC clock
Output Watchdog Timer - WDT
WDTEXT
External Watchdog Pin
Output External Interrupt Controller - EIC
EXTINT0 - EXTINT7 KPS0 - KPS7 NMI_N
External Interrupt Pins Keypad Scan Pins Non-Maskable Interrupt Pin
Input Output Input Ethernet MAC - MACB Low
COL CRS MDC MDIO RXD0 - RXD3 RX_CLK RX_DV RX_ER SPEED TXD0 - TXD3 TX_CLK TX_EN TX_ER
Collision Detect Carrier Sense and Data Valid Management Data Clock Management Data Input/Output Receive Data Receive Clock Receive Data Valid Receive Coding Error Speed Transmit Data Transmit Clock or Reference Clock Transmit Enable Transmit Coding Error
Input Input Output I/O Input Input Input Input
Output Output Output Output
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Table 5-1.
Signal Name
Signal Description List
Function Type External Bus Interface - HEBI Active Level Comments
ADDR0 - ADDR23 CAS DATA0 - DATA15 NCS0 - NCS3 NRD NWAIT NWE0 NWE1 NWE3 RAS SDA10 SDCK SDCKE SDCS0 SDWE
Address Bus Column Signal Data Bus Chip Select Read Signal External Wait Signal Write Enable 0 Write Enable 1 Write Enable 3 Row Signal SDRAM Address 10 Line SDRAM Clock SDRAM Clock Enable SDRAM Chip Select SDRAM Write Enable
Output Output I/O Output Output Input Output Output Output Output Output Output Output Output Output Low Low Low Low Low Low Low Low Low Low
General Purpose Input/Output 2 - GPIOA, GPIOB, GPIOC P0 - P31 P0 - P31 P0 - P5 P0 - P31 Parallel I/O Controller GPIOA Parallel I/O Controller GPIOB Parallel I/O Controller GPIOC Parallel I/O Controller GPIOX I/O I/O I/O I/O
Serial Peripheral Interface - SPI0, SPI1 MISO MOSI NPCS0 - NPCS3 SCK Master In Slave Out Master Out Slave In SPI Peripheral Chip Select Clock I/O I/O I/O Output Synchronous Serial Controller - SSC RX_CLOCK SSC Receive Clock I/O Low
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Table 5-1.
Signal Name RX_DATA RX_FRAME_SYNC TX_CLOCK TX_DATA TX_FRAME_SYNC
Signal Description List
Function SSC Receive Data SSC Receive Frame Sync SSC Transmit Clock SSC Transmit Data SSC Transmit Frame Sync Type Input I/O I/O Output I/O Timer/Counter - TIMER Active Level Comments
A0 A1 A2 B0 B1 B2 CLK0 CLK1 CLK2
Channel 0 Line A Channel 1 Line A Channel 2 Line A Channel 0 Line B Channel 1 Line B Channel 2 Line B Channel 0 External Clock Input Channel 1 External Clock Input Channel 2 External Clock Input
I/O I/O I/O I/O I/O I/O Input Input Input
Two-wire Interface - TWI SCL SDA Serial Clock Serial Data I/O I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3 CLK CTS DCD DSR DTR RI RTS RXD TXD Clock Clear To Send Data Carrier Detect Data Set Ready Data Terminal Ready Ring Indicator Request To Send Receive Data Transmit Data Output Input Output I/O Input Only USART1 Only USART1 Only USART1 Only USART1
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Table 5-1.
Signal Name
Signal Description List
Function Type Analog to Digital Converter - ADC Active Level Comments
AD0 - AD7
Analog input pins
Analog input Analog input 2.6 to 3.6V
ADVREF
Analog positive reference voltage input
Pulse Width Modulator - PWM PWM0 - PWM6 PWM Output Pins Output Universal Serial Bus Device - USB DDM DDP VBUS USBID USB_VBOF USB Device Port Data USB Device Port Data + USB VBUS Monitor and OTG Negociation ID Pin of the USB Bus USB VBUS On/off: bus power control port Analog Analog Analog Input Input output
Audio Bitstream DAC (ABDAC) DATA0-DATA1 DATAN0-DATAN1 D/A Data out D/A Data inverted out Outpu Outpu
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6. Package and Pinout
The device pins are multiplexed with peripheral functions as described in "Peripheral Multiplexing on I/O lines" on page 30. Figure 6-1. TQFP100 Pinout
75 76
51 50
100 1 25
26
Table 6-1.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
TQFP100 Package Pinout
PB20 PB21 PB22 VDDIO GND PB23 PB24 PB25 PB26 PB27 VDDOUT VDDIN GND PB28 PB29 PB30 PB31 RESET_N PA00 PA01 GND VDDCORE 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 PA05 PA06 PA07 PA08 PA09 PA10 N/C PA11 VDDCORE GND PA12 PA13 VDDCORE PA14 PA15 PA16 PA17 PA18 PA19 PA20 VBUS VDDIO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 VDDANA ADVREF GNDANA VDDPLL PC00 PC01 PB00 PB01 VDDIO VDDIO GND PB02 PB03 PB04 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 PB08 PB09 PB10 VDDIO GND PB11 PB12 PA29 PA30 PC02 PC03 PB13 PB14 TMS TCK TDO TDI PC04 PC05 PB15 PB16 VDDCORE
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Table 6-1.
23 24 25
TQFP100 Package Pinout
PA02 PA03 PA04 48 49 50 DM DP GND 73 74 75 PB05 PB06 PB07 98 99 100 PB17 PB18 PB19
Figure 6-2.
LQFP144 Pinout
108 109
73 72
144 1 36
37
Table 6-2.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
VQFP144 Package Pinout
PX00 PX01 PB20 PX02 PB21 PB22 VDDIO GND PB23 PX03 PB24 PX04 PB25 PB26 PB27 VDDOUT VDDIN GND PB28 PB29 PB30 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 GND PX10 PA05 PX11 PA06 PX12 PA07 PX13 PA08 PX14 PA09 PA10 N/C PA11 VDDCORE GND PA12 PA13 VDDCORE PA14 PA15 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 VDDANA ADVREF GNDANA VDDPLL PC00 PC01 PX20 PB00 PX21 PB01 PX22 VDDIO VDDIO 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 GND PX30 PB08 PX31 PB09 PX32 PB10 VDDIO GND PX33 PB11 PX34 PB12 PA29 PA30 PC02 PC03 PB13 PB14 TMS TCK
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Table 6-2.
22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
VQFP144 Package Pinout
PB31 RESET_N PX05 PA00 PX06 PA01 GND VDDCORE PA02 PX07 PA03 PX08 PA04 PX09 VDDIO 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 PA16 PX15 PA17 PX16 PA18 PX17 PA19 PX18 PA20 PX19 VBUS VDDIO DM DP GND 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 GND PX23 PB02 PX24 PB03 PX25 PB04 PX26 PB05 PX27 PB06 PX28 PB07 PX29 VDDIO 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 TDO TDI PC04 PC05 PB15 PX35 PB16 PX36 VDDCORE PB17 PX37 PB18 PX38 PB19 PX39
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7. Power Considerations
7.1 Power Supplies
The AT32UC3A has several types of power supply pins: * * * * *
VDDIO: Powers I/O lines. Voltage is 3.3V nominal. VDDANA: Powers the ADC Voltage is 3.3V nominal. VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V nominal. VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.8V nominal. VDDPLL: Powers the PLL. Voltage is 1.8V nominal.
The ground pins GND are common to VDDCORE, VDDIO, VDDPLL. The ground pin for VDDANA is GNDANA. Refer to "Power Consumption" on page 42 for power consumption on the various supply pins.
Dual Power Supply Single Power Supply 3.3V VDDANA 3.3V VDDANA
VDDIO
VDDIO
ADVREF
ADVREF
VDDIN
1.8V Regulator
VDDIN
1.8V Regulator
VDDOUT
VDDOUT
VDDCORE
1.8V
VDDCORE
VDDPLL
VDDPLL
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7.2
7.2.1
Voltage Regulator
Single Power Supply The AT32UC3A embeds a voltage regulator that converts from 3.3V to 1.8V. The regulator takes its input voltage from VDDIN, and supplies the output voltage on VDDOUT. VDDOUT should be externally connected to the 1.8V domains. Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. Two input decoupling capacitors must be placed close to the chip. Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel between VDDOUT and GND as close to the chip as possible
3.3V CIN2 CIN1
VDDIN
1.8V Regulator
VDDOUT
1.8V COUT2 COUT1
Refer to Section 12.3 on page 41 for decoupling capacitors values and regulator characteristics
7.2.2
Dual Power Supply In case of dual power supply, VDDIN and VDDOUT should be connected to ground to prevent from leakage current.
VDDIN
VDDOUT
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7.3 Analog-to-Digital Converter (A.D.C) reference.
The ADC reference (ADVREF) must be provided from an external source. Two decoupling capacitors must be used to insure proper decoupling.
3.3V C
VREF2
ADVREF C
VREF1
Refer to Section 12.4 on page 41 for decoupling capacitors values and electrical characteristics. In case ADC is not used, the ADVREF pin should be connected to GND to avoid extra consumption.
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8. I/O Line Considerations
8.1 JTAG pins
TMS, TDI and TCK have pull-up resistors. TDO is an output, driven at up to VDDIO, and has no pull-up resistor.
8.2
RESET_N pin
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIO. As the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case no reset from the system needs to be applied to the product.
8.3
TWI pins
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with inputs with spike-filtering. When used as GPIO-pins or used for other peripherals, the pins have the same characteristics as PIO pins.
8.4
GPIO pins
All the I/O lines integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as inputs with pull-up resistors disabled, except when indicated otherwise in the column "Reset State" of the GPIO Controller multiplexing tables.
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9. Memories
9.1 Embedded Memories
* Internal High-Speed Flash
- 512 KBytes (AT32UC3A0512, AT32UC3A1512) - 256 KBytes (AT32UC3A0256, AT32UC3A1256) - 128 KBytes (AT32UC3A1128, AT32UC3A2128) - 0 Wait State Access at up to 33 MHz in Worst Case Conditions - 1 Wait State Access at up to 66 MHz in Worst Case Conditions - Pipelined Flash Architecture, allowing burst reads from sequential Flash locations, hiding penalty of 1 wait state access - Pipelined Flash Architecture typically reduces the cycle penalty of 1 wait state operation to only 15% compared to 0 wait state operation - 100 000 Write Cycles, 15-year Data Retention Capability - 4 ms Page Programming Time, 8 ms Chip Erase Time - Sector Lock Capabilities, Bootloader Protection, Security Bit - 32 Fuses, Erased During Chip Erase - User Page For Data To Be Preserved During Chip Erase * Internal High-Speed SRAM, Single-cycle access at full speed - 64 KBytes (AT32UC3A0512, AT32UC3A0256, AT32UC3A1512, AT32UC3A1256) - 32KBytes (AT32UC3A1128)
9.2
Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they are never remapped in any way, not even in boot. Note that AVR32 UC CPU uses unsegmented translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space is mapped as follows:
Table 9-1.
Device
AT32UC3A Physical Memory Map
Start Address 0x0000_0000 0x8000_0000 0xC000_0000 0xC800_0000 0xCC00_0000 0xD000_0000 0xE000_0000 0xFFFE_0000 0xFFFF_0000 Size
AT32UC3A0512 AT32UC3A1512 AT32UC3A0256 AT32UC3A1256 AT32UC3A0128 AT32UC3A1128
Embedded SRAM Embedded Flash EBI SRAM CS0 EBI SRAM CS2 EBI SRAM CS3 EBI SRAM CS1 /SDRAM CS0 USB Configuration HSB-PB Bridge A HSB-PB Bridge B
64 Kbyte 512 Kbyte 16 Mbyte 16 Mbyte 16 Mbyte 128 Mbyte 64 Kbyte 64 Kbyte 64 Kbyte
64 Kbyte 512 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte
64 Kbyte 256 Kbyte 16 Mbyte 16 Mbyte 16 Mbyte 128 Mbyte 64 Kbyte 64 Kbyte 64 kByte
64 Kbyte 256 Kbyte 64 Kbyte 64 Kbyte 64 kByte
32 Kbyte 128 Kbyte 16 Mbyte 16 Mbyte 16 Mbyte 128 Mbyte 64 Kbyte 64 Kbyte 64 Kbyte
32 Kbyte 128 Kbyte 64 Kbyte 64 Kbyte 64 Kbyte
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Table 9-2.
Flash Memory Parameters
Flash Size (FLASH_PW) 512 Kbytes 512 Kbytes 256 Kbytes 256 Kbytes 128 Kbytes 128 Kbytes Number of pages (FLASH_P) 1024 1024 512 512 64 64 Page size (FLASH_W) 128 words 128 words 128 words 128 words 128 words 128 words General Purpose Fuse bits (FLASH_F) 32 fuses 32 fuses 32 fuses 32 fuses 32 fuses 32 fuses
Part Number AT32UC3A0512 AT32UC3A1512 AT32UC3A0256 AT32UC3A1256 AT32UC3A1128 AT32UC3A0128
9.3
Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access. The bus matrix has the several masters and slaves. Each master has its own bus and its own decoder, thus allowing a different memory mapping per master. The master number in the table below can be used to index the HMATRIX control registers. For example, MCFG0 is associated with the CPU Data master interface. Table 9-3.
Master 0 Master 1 Master 2 Master 3 Master 4 Master 5
High Speed Bus masters
CPU Data CPU Instruction CPU SAB PDCA MACB DMA USBB DMA
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is associated with the Internal SRAM Slave Interface. Table 9-4.
Slave 0 Slave 1 Slave 2 Slave 3 Slave 4 Slave 5
High Speed Bus slaves
Internal Flash HSB-PB Bridge 0 HSB-PB Bridge 1 Internal SRAM USBB DPRAM EBI
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Figure 9-1. HMatrix Master / Slave Connections
HMATRIX SLAVES Internal SRAM Slave
Internal Flash
USBB Slave
HSB-PB Bridge 0
HSB-PB Bridge 1
0
1
2
3
4
CPU Data
0
CPU Instruction HMATRIX MASTERS
1
CPU SAB
2
PDCA
3
MACB
4
USBB DMA
5
EBI 5
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10. Peripherals
10.1 Peripheral address map
Peripheral Address Mapping
Address Peripheral Name Bus
Table 10-1.
0xE0000000
USBB
USBB Slave Interface - USBB
HSB
0xFFFE0000
USBB
USBB Configuration Interface - USBB
PBB
0xFFFE1000
HMATRIX
HMATRIX Configuration Interface - HMATRIX
PBB
0xFFFE1400
FLASHC
Flash Controller - FLASHC
PBB
0xFFFE1800
MACB
MACB Configuration Interface - MACB Static Memory Controller Configuration Interface SMC SDRAM Controller Configuration Interface SDRAMC Peripheral DMA Interface - PDCA
PBB
0xFFFE1C00
SMC
PBB
0xFFFE2000
SDRAMC
PBB
0xFFFF0000
PDCA
PBA
0xFFFF0800
INTC
Interrupt Controller Interface - INTC
PBA
0xFFFF0C00
PM
Power Manager - PM
PBA
0xFFFF0D00
RTC
Real Time Clock - RTC
PBA
0xFFFF0D30
WDT
WatchDog Timer - WDT
PBA
0xFFFF0D80
EIC
External Interrupt Controller - EIC
PBA
0xFFFF1000
GPIO
General Purpose IO Controller - GPIO Universal Synchronous Asynchronous Receiver Transmitter - USART0 Universal Synchronous Asynchronous Receiver Transmitter - USART1
PBA
0xFFFF1400
USART0
PBA
0xFFFF1800
USART1
PBA
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Table 10-1. Peripheral Address Mapping (Continued)
Address Peripheral Name Bus
0xFFFF1C00
USART2
Universal Synchronous Asynchronous Receiver Transmitter - USART2 Universal Synchronous Asynchronous Receiver Transmitter - USART3 Serial Peripheral Interface - SPI0
PBA
0xFFFF2000
USART3
PBA
0xFFFF2400
SPI0
PBA
0xFFFF2800
SPI1
Serial Peripheral Interface - SPI1
PBA
0xFFFF2C00
TWI
Two Wire Interface - TWI
PBA
0xFFFF3000
PWM
Pulse Width Modulation Controller - PWM
PBA
0xFFFF3400
SSC
Synchronous Serial Controller - SSC
PBA
0xFFFF3800
TC
Timer/Counter - TC
PBA
0xFFFF3C00
ADC
Analog To Digital Converter - ADC
PBA
10.2
CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus. Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at CPU speed, one write or read operation can be performed per clock cycle to the local busmapped GPIO registers.
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The following GPIO registers are mapped on the local bus: Table 10-2.
Port 0
Local bus mapped GPIO registers
Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x4000_0040 0x4000_0044 0x4000_0048 0x4000_004C 0x4000_0050 0x4000_0054 0x4000_0058 0x4000_005C 0x4000_0060 0x4000_0140 0x4000_0144 0x4000_0148 0x4000_014C 0x4000_0150 0x4000_0154 0x4000_0158 0x4000_015C 0x4000_0160 0x4000_0240 0x4000_0244 0x4000_0248 0x4000_024C 0x4000_0250 0x4000_0254 0x4000_0258 0x4000_025C 0x4000_0260 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only
Register Output Driver Enable Register (ODER)
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR) 1 Output Driver Enable Register (ODER)
WRITE SET CLEAR TOGGLE
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR) 2 Output Driver Enable Register (ODER)
WRITE SET CLEAR TOGGLE
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR)
-
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Table 10-2.
Port 3
Local bus mapped GPIO registers
Mode WRITE SET CLEAR TOGGLE Local Bus Address 0x4000_0340 0x4000_0344 0x4000_0348 0x4000_034C 0x4000_0350 0x4000_0354 0x4000_0358 0x4000_035C 0x4000_0360 Access Write-only Write-only Write-only Write-only Write-only Write-only Write-only Write-only Read-only
Register Output Driver Enable Register (ODER)
Output Value Register (OVR)
WRITE SET CLEAR TOGGLE
Pin Value Register (PVR)
-
10.3
Interrupt Request Signal Map
The various modules may output Interrupt request signals. These signals are routed to the Interrupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64 groups of interrupt requests. Each group can have up to 32 interrupt request signals. All interrupt signals in the same group share the same autovector address and priority level. Refer to the documentation for the individual submodules for a description of the semantics of the different interrupt requests. The interrupt request signals are connected to the INTC as follows. Table 10-3.
Group 0
Interrupt Request Signal Map
Line 0 0 1 2 3 4 Module AVR32 UC CPU with optional MPU and optional OCD External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller External Interrupt Controller Real Time Counter Power Manager Frequency Meter Signal SYSBLOCK COMPARE EIC 0 EIC 1 EIC 2 EIC 3 EIC 4 EIC 5 EIC 6 EIC 7 RTC PM FREQM
1
5 6 7 8 9 10
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Table 10-3. Interrupt Request Signal Map
0 1 2 3 4 5 6 2 7 8 9 10 11 12 13 0 1 2 3 4 5 6 3 7 8 9 10 11 12 13 14 4 5 6 7 8 0 0 0 0 0 General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Peripheral DMA Controller Flash Controller Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter Universal Synchronous/Asynchronous Receiver/Transmitter GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 PDCA 0 PDCA 1 PDCA 2 PDCA 3 PDCA 4 PDCA 5 PDCA 6 PDCA 7 PDCA 8 PDCA 9 PDCA 10 PDCA 11 PDCA 12 PDCA 13 PDCA 14 FLASHC USART0 USART1 USART2 USART3 General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output General Purpose Input/Output GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6
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Table 10-3.
9 10 11 12 13
Interrupt Request Signal Map
0 0 0 0 0 0 Serial Peripheral Interface Serial Peripheral Interface Two-wire Interface Pulse Width Modulation Controller Synchronous Serial Controller Timer/Counter Timer/Counter Timer/Counter Analog to Digital Converter Ethernet MAC USB 2.0 OTG Interface SDRAM Controller Audio Bitstream DAC SPI0 SPI1 TWI PWM SSC TC0 TC1 TC2 ADC MACB USBB SDRAMC DAC
14
1 2
15 16 17 18 19
0 0 0 0 0
10.4
10.4.1
Clock Connections
Timer/Counters Each Timer/Counter channel can independently select an internal or external clock source for its counter: Table 10-4.
Source Internal
Timer/Counter clock connections
Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Connection 32 KHz Oscillator PBA clock / 2 PBA clock / 8 PBA clock / 32 PBA clock / 128 See Section 10.7
External
XC0 XC1 XC2
10.4.2
USARTs Each USART can be connected to an internally divided clock: Table 10-5.
USART 0 1 2 3
USART clock connections
Source Internal Name CLK_DIV Connection PBA clock / 8
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10.4.3 SPIs Each SPI can be connected to an internally divided clock: Table 10-6.
SPI 0 1
SPI clock connections
Source Internal Name CLK_DIV Connection PBA clock or PBA clock / 32
10.5
Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irrespectively of the PIO configuration. Two different OCD trace pin mappings are possible, depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Technical Reference Manual. Table 10-7.
Pin EVTI_N MDO[5] MDO[4] MDO[3] MDO[2] MDO[1] MDO[0] EVTO_N MCKO MSEO[1] MSEO[0]
Nexus OCD AUX port connections
AXS=0 PB19 PB16 PB14 PB13 PB12 PB11 PB10 PB20 PB21 PB04 PB17 AXS=1 PA08 PA27 PA26 PA25 PA24 PA23 PA22 PB20 PA21 PA07 PA28
10.6
PDC handshake signals
The PDC and the peripheral modules communicate through a set of handshake signals. The following table defines the valid settings for the Peripheral Identifier (PID) in the PDC Peripheral Select Register (PSR).
Table 10-8.
PID Value 0 1 2 3
PDC Handshake Signals
Peripheral module & direction ADC SSC - RX USART0 - RX USART1 - RX
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Table 10-8.
PID Value 4 5 6 7 8 9 10 11 12 13 14 15 16 17
PDC Handshake Signals
Peripheral module & direction USART2 - RX USART3 - RX TWI - RX SPI0 - RX SPI1 - RX SSC - TX USART0 - TX USART1 - TX USART2 - TX USART3 - TX TWI - TX SPI0 - TX SPI1 - TX ABDAC
10.7
Peripheral Multiplexing on I/O lines
Each GPIO line can be assigned to one of 3 peripheral functions; A, B or C. The following table define how the I/O lines on the peripherals A, B and C are multiplexed by the GPIO.
Table 10-9.
TQFP100 19 20 23 24 25 26 27 28 29 30 31 33 36 37 39 40
GPIO Controller Function Multiplexing
VQFP144 25 27 30 32 34 39 41 43 45 47 48 50 53 54 56 57 PIN PA00 PA01 PA02 PA03 PA04 PA05 PA06 PA07 PA08 PA09 PA10 PA11 PA12 PA13 PA14 PA15 GPIO Pin GPIO 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 GPIO 6 GPIO 7 GPIO 8 GPIO 9 GPIO 10 GPIO 11 GPIO 12 GPIO 13 GPIO 14 GPIO 15 Function A USART0 - RXD USART0 - TXD USART0 - CLK USART0 - RTS USART0 - CTS USART1 - RXD USART1 - TXD USART1 - CLK USART1 - RTS USART1 - CTS SPI0 - NPCS[0] SPI0 - MISO SPI0 - MOSI SPI0 - SCK SSC TX_FRAME_SYNC SSC - TX_CLOCK SPI1 - NPCS[0] SPI1 - SCK EBI - NCS[0] EBI - ADDR[20] Function B TC - CLK0 TC - CLK1 TC - CLK2 EIM - EXTINT[4] EIM - EXTINT[5] PWM - PWM[4] PWM - PWM[5] PM - GCLK[0] SPI0 - NPCS[1] SPI0 - NPCS[2] EIM - EXTINT[6] USB - USB_ID USB - USB_VBOF SPI0 - NPCS[3] EIM - EXTINT[7] MACB - WOL DAC - DATA[0] DAC - DATAN[0] Function C
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Table 10-9.
41 42 43 44 45 51 52 53 54 55 56 57 58 83 84 65 66 70 71 72 73 74 75 76 77 78 81 82 87 88 95 96 98 99 100 1 2 3 6
GPIO Controller Function Multiplexing
58 60 62 64 66 73 74 75 76 77 78 79 80 122 123 88 90 96 98 100 102 104 106 111 113 115 119 121 126 127 134 136 139 141 143 3 5 6 9 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PB00 PB01 PB02 PB03 PB04 PB05 PB06 PB07 PB08 PB09 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 GPIO 16 GPIO 17 GPIO 18 GPIO 19 GPIO 20 GPIO 21 GPIO 22 GPIO 23 GPIO 24 GPIO 25 GPIO 26 GPIO 27 GPIO 28 GPIO 29 GPIO 30 GPIO 32 GPIO 33 GPIO 34 GPIO 35 GPIO 36 GPIO 37 GPIO 38 GPIO 39 GPIO 40 GPIO 41 GPIO 42 GPIO 43 GPIO 44 GPIO 45 GPIO 46 GPIO 47 GPIO 48 GPIO 49 GPIO 50 GPIO 51 GPIO 52 GPIO 53 GPIO 54 GPIO 55 SSC - TX_DATA SSC - RX_DATA SSC - RX_CLOCK SSC RX_FRAME_SYNC EIM - EXTINT[8] ADC - AD[0] ADC - AD[1] ADC - AD[2] ADC - AD[3] ADC - AD[4] ADC - AD[5] ADC - AD[6] ADC - AD[7] TWI - SDA TWI - SCL MACB - TX_CLK MACB - TX_EN MACB - TXD[0] MACB - TXD[1] MACB - CRS MACB - RXD[0] MACB - RXD[1] MACB - RX_ER MACB - MDC MACB - MDIO MACB - TXD[2] MACB - TXD[3] MACB - TX_ER MACB - RXD[2] MACB - RXD[3] MACB - RX_DV MACB - COL MACB - RX_CLK MACB - SPEED PWM - PWM[0] PWM - PWM[1] PWM - PWM[2] PWM - PWM[3] TC - A0 USB - USB_ID USB - USB_VBOF ADC - TRIGGER PM - GCLK[0] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] USART1 - DCD EBI - SDA10 EBI - ADDR[23] PWM - PWM[6] EIM - SCAN[4] EIM - SCAN[5] EIM - SCAN[6] EIM - SCAN[7] USART3 - RXD USART3 - TXD TC - CLK0 TC - CLK1 TC - CLK2 EBI - SDCK EBI - SDCKE EBI - RAS EBI - CAS EBI - SDWE SPI1 - MOSI SPI1 - MISO SPI1 - NPCS[1] SPI1 - NPCS[2] SPI1 - NPCS[3] EIM - EXTINT[0] EIM - EXTINT[1] EIM - EXTINT[2] EIM - EXTINT[3] EIM - SCAN[0] EIM - SCAN[1] EIM - SCAN[2] EIM - SCAN[3] USART2 - RTS USART2 - CTS USART2 - RTS USART2 - CTS DAC - DATA[0] DAC - DATAN[0] USART3 - CLK DAC - DATA[1] DAC - DATAN[1] EBI - NCS[3] USART3 - RTS USART3 - CTS USB - USB_ID USB - USB_VBOF DAC - DATA[1] DAC - DATAN[1] EBI - NCS[0] EBI - ADDR[20] EBI - ADDR[21] EBI - ADDR[22] EBI - ADDR[21] EBI - ADDR[22] MACB - WOL
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Table 10-9.
7 8 9 10 14 15 16 17 63 64 85 86 93 94
GPIO Controller Function Multiplexing
11 13 14 15 19 20 21 22 85 86 124 125 132 133 1 2 4 10 12 24 26 31 33 35 38 40 42 44 46 59 61 63 65 67 87 89 91 95 97 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31 PC00 PC01 PC02 PC03 PC04 PC05 PX00 PX01 PX02 PX03 PX04 PX05 PX06 PX07 PX08 PX09 PX10 PX11 PX12 PX13 PX14 PX15 PX16 PX17 PX18 PX19 PX20 PX21 PX22 PX23 PX24 GPIO 56 GPIO 57 GPIO 58 GPIO 59 GPIO 60 GPIO 61 GPIO 62 GPIO 63 GPIO 64 GPIO 65 GPIO 66 GPIO 67 GPIO 68 GPIO 69 GPIO 100 GPIO 99 GPIO 98 GPIO 97 GPIO 96 GPIO 95 GPIO 94 GPIO 93 GPIO 92 GPIO 91 GPIO 90 GPIO 109 GPIO 108 GPIO 107 GPIO 106 GPIO 89 GPIO 88 GPIO 87 GPIO 86 GPIO 85 GPIO 84 GPIO 83 GPIO 82 GPIO 81 GPIO 80 EBI - DATA[10] EBI - DATA[9] EBI - DATA[8] EBI - DATA[7] EBI - DATA[6] EBI - DATA[5] EBI - DATA[4] EBI - DATA[3] EBI - DATA[2] EBI - DATA[1] EBI - DATA[0] EBI - NWE1 EBI - NWE0 EBI - NRD EBI - NCS[1] EBI - ADDR[19] EBI - ADDR[18] EBI - ADDR[17] EBI - ADDR[16] EBI - ADDR[15] EBI - ADDR[14] EBI - ADDR[13] EBI - ADDR[12] EBI - ADDR[11] EBI - ADDR[10] EIM - SCAN[0] EIM - SCAN[1] EIM - SCAN[2] EIM - SCAN[3] EIM - SCAN[4] EIM - SCAN[5] USART3 - RTS USART3 - CTS USART0 - RXD USART0 - TXD USART0 - CTS USART0 - RTS USART1 - RXD USART1 - TXD USART1 - CTS USART1 - RTS USART3 - RXD USART3 - TXD USART2 - RXD USART2 - TXD USART2 - CTS USART2 - RTS TC - A0 TC - B0 TC - A1 TC - B1 TC - A2 TC - B2 TC - CLK0 TC - CLK1 TC - CLK2 TC - B0 TC - A1 TC - B1 TC - A2 TC - B2 USART2 - RXD USART2 - TXD USART2 - CLK USART1 - DSR USART1 - DTR USART1 - RI PWM - PWM[4] PWM - PWM[5] PM - GCLK[1] PM - GCLK[2] PM - GCLK[3] EBI - NCS[2] EBI - SDCS EBI - NWAIT
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Table 10-9. GPIO Controller Function Multiplexing
99 101 103 105 107 110 112 114 118 120 135 137 140 142 144 PX25 PX26 PX27 PX28 PX29 PX30 PX31 PX32 PX33 PX34 PX35 PX36 PX37 PX38 PX39 GPIO 79 GPIO 78 GPIO 77 GPIO 76 GPIO 75 GPIO 74 GPIO 73 GPIO 72 GPIO 71 GPIO 70 GPIO 105 GPIO 104 GPIO 103 GPIO 102 GPIO 101 EBI - ADDR[9] EBI - ADDR[8] EBI - ADDR[7] EBI - ADDR[6] EBI - ADDR[5] EBI - ADDR[4] EBI - ADDR[3] EBI - ADDR[2] EBI - ADDR[1] EBI - ADDR[0] EBI - DATA[15] EBI - DATA[14] EBI - DATA[13] EBI - DATA[12] EBI - DATA[11] EIM - SCAN[6] EIM - SCAN[7] SPI0 - MISO SPI0 - MOSI SPI0 - SCK SPI0 - NPCS[0] SPI0 - NPCS[1] SPI0 - NPCS[2] SPI0 - NPCS[3] SPI1 - MISO SPI1 - MOSI SPI1 - SCK SPI1 - NPCS[0] SPI1 - NPCS[1] SPI1 - NPCS[2]
10.8
Oscillator Pinout
The oscillators are not mapped to the normal A,B or C functions and their muxings are controlled by registers in the Power Manager (PM). Please refer to the power manager chapter for more information about this. Table 10-10. Oscillator pinout
TQFP100 pin 85 93 63 86 94 64 VQFP144 pin 124 132 85 125 133 86 Pad PC02 PC04 PC00 PC03 PC05 PC01 Oscillator pin xin0 xin1 xin32 xout0 xout1 xout32
10.9
USART Configuration
Table 10-11. USART Supported Mode
SPI USART0 USART1 USART2 USART3 Yes Yes Yes Yes RS485 No Yes No No ISO7816 No Yes No No IrDA No Yes No No Modem No Yes No No Manchester Encoding No Yes No No
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10.10 GPIO
The GPIO open drain feature (GPIO ODMER register (Open Drain Mode Enable Register)) is not available for this device.
10.11 Peripheral overview
10.11.1 External Bus Interface * Optimized for Application Memory Space support * Integrates Two External Memory Controllers:
- Static Memory Controller - SDRAM Controller * Optimized External Bus: - 16-bit Data Bus - 24-bit Address Bus, Up to 16-Mbytes Addressable - Optimized pin multiplexing to reduce latencies on External Memories * 4 SRAM Chip Selects, 1SDRAM Chip Select: - Static Memory Controller on NCS0 - SDRAM Controller or Static Memory Controller on NCS1 - Static Memory Controller on NCS2 - Static Memory Controller on NCS3
10.11.2
Static Memory Controller * 4 Chip Selects Available * 64-Mbyte Address Space per Chip Select * 8-, 16-bit Data Bus * Word, Halfword, Byte Transfers * Byte Write or Byte Select Lines * Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select * Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select * Programmable Data Float Time per Chip Select * Compliant with LCD Module * External Wait Request * Automatic Switch to Slow Clock Mode * Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes SDRAM Controller * Numerous Configurations Supported
- 2K, 4K, 8K Row Address Memory Parts - SDRAM with Two or Four Internal Banks - SDRAM with 16-bit Data Path * Programming Facilities - Word, Half-word, Byte Access - Automatic Page Break When Memory Boundary Has Been Reached - Multibank Ping-pong Access - Timing Parameters Specified by Software - Automatic Refresh Operation, Refresh Rate is Programmable * Energy-saving Capabilities - Self-refresh, Power-down and Deep Power Modes Supported
10.11.3
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- Supports Mobile SDRAM Devices
* Error Detection
- Refresh Error Interrupt * SDRAM Power-up Initialization by Software * CAS Latency of 1, 2, 3 Supported * Auto Precharge Command Not Used
10.11.4
USB Controller * USB 2.0 Compliant, Full-/Low-Speed (FS/LS) and On-The-Go (OTG), 12 Mbit/s * 7 Pipes/Endpoints * 960 bytes of Embedded Dual-Port RAM (DPRAM) for Pipes/Endpoints * Up to 2 Memory Banks per Pipe/Endpoint (Not for Control Pipe/Endpoint) * Flexible Pipe/Endpoint Configuration and Management with Dedicated DMA Channels * On-Chip Transceivers Including Pull-Ups Serial Peripheral Interface * Supports communication with serial external devices
- Four chip selects with external decoder support allow communication with up to 15 peripherals - Serial memories, such as DataFlash and 3-wire EEPROMs - Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and Sensors - External co-processors * Master or slave serial peripheral bus interface - 8- to 16-bit programmable data length per chip select - Programmable phase and polarity per chip select - Programmable transfer delays between consecutive transfers and between clock and data per chip select - Programmable delay between consecutive transfers - Selectable mode fault detection * Very fast transfers supported - Transfers with baud rates up to Peripheral Bus A (PBA) max frequency - The chip select line may be left active to speed up transfers on the same device
10.11.5
10.11.6
Two-wire Interface * * * *
High speed up to 400kbit/s Compatibility with standard two-wire serial memory One, two or three bytes for slave address Sequential read/write operations
10.11.7
USART * Programmable Baud Rate Generator * 5- to 9-bit full-duplex synchronous or asynchronous serial communications
- - - - - - - - - 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode Parity generation and error detection Framing error detection, overrun error detection MSB- or LSB-first Optional break generation and detection By 8 or by-16 over-sampling receiver frequency Hardware handshaking RTS-CTS Receiver time-out and transmitter timeguard Optional Multi-drop Mode with address generation and detection
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- Optional Manchester Encoding
* RS485 with driver control signal * ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards
- NACK handling, error counter with repetition and iteration limit
* IrDA modulation and demodulation
- Communication at up to 115.2 Kbps * Test Modes - Remote Loopback, Local Loopback, Automatic Echo * SPI Mode - Master or Slave - Serial Clock Programmable Phase and Polarity - SPI Serial Clock (SCK) Frequency up to Internal Clock Frequency PBA/4 * Supports Connection of Two Peripheral DMA Controller Channels (PDC) - Offers Buffer Transfer without Processor Intervention
10.11.8
Serial Synchronous Controller * Provides serial synchronous communication links used in audio and telecom applications (with
CODECs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)
* Contains an independent receiver and transmitter and a common clock divider * Offers a configurable frame sync and data length * Receiver and transmitter can be programmed to start automatically or on detection of different
event on the frame sync signal * Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal
10.11.9
Timer Counter * Three 16-bit Timer Counter Channels * Wide range of functions including:
- Frequency Measurement - Event Counting - Interval Measurement - Pulse Generation - Delay Timing - Pulse Width Modulation - Up/down Capabilities * Each channel is user-configurable and contains: - Three external clock inputs - Five internal clock inputs - Two multi-purpose input/output signals * Two global registers that act on all three TC Channels
10.11.10 Pulse Width Modulation Controller * 7 channels, one 20-bit counter per channel * Common clock generator, providing Thirteen Different Clocks
- A Modulo n counter providing eleven clocks - Two independent Linear Dividers working on modulo n counter outputs * Independent channel programming - Independent Enable Disable Commands - Independent Clock - Independent Period and Duty Cycle, with Double Bufferization - Programmable selection of the output waveform polarity - Programmable center or left aligned output waveform
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10.11.11 Ethernet 10/100 MAC * * * * * * * * * * * *
Compatibility with IEEE Standard 802.3 10 and 100 Mbits per second data throughput capability Full- and half-duplex operations MII or RMII interface to the physical layer Register Interface to address, data, status and control registers DMA Interface, operating as a master on the Memory Controller Interrupt generation to signal receive and transmit completion 28-byte transmit and 28-byte receive FIFOs Automatic pad and CRC generation on transmitted frames Address checking logic to recognize four 48-bit addresses Support promiscuous mode where all valid frames are copied to memory Support physical layer management through MDIO interface control of alarm and update time/calendar data
10.11.12 Audio Bitstream DAC * Digital Stereo DAC * Oversampled D/A conversion architecture
- Oversampling ratio fixed 128x - FIR equalization filter - Digital interpolation filter: Comb4 - 3rd Order Sigma-Delta D/A converters * Digital bitstream outputs * Parallel interface * Connected to Peripheral DMA Controller for background transfer without CPU intervention
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11. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3A. The behaviour after power-up is controlled by the Power Manager. For specific details, refer to Section 13. "Power Manager (PM)" on page 55.
11.1
Starting of clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the power has stabilized throughout the device. Once the power has stabilized, the device will use the internal RC Oscillator as clock source. On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have a divided frequency, all parts of the system recieves a clock with the same frequency as the internal RC Oscillator.
11.2
Fetching of initial instructions
After reset has been released, the AVR32 UC CPU starts fetching instructions from the reset address, which is 0x8000_0000. This address points to the first address in the internal Flash. The code read from the internal Flash is free to configure the system to use for example the PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.
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12. Electrical Characteristics
12.1 Absolute Maximum Ratings*
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature......................................-40C to +85C Storage Temperature .......................................................... ....60C to +150C Voltage on Input Pin with respect to Ground-O.3V to 5.5V
Maximum Operating Voltage (VDDCORE, VDDPLL) ..... 1.95V Maximum Operating Voltage (VDDIO).............................. 3.6V Total DC Output Current on all I/O Pin for TQFP100 packag ................................................... 370 mA for LQGP144 package ................................................. 470 mA
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12.2 DC Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C, unless otherwise specified and are certified for a junction temperature up to TJ = 100C.
Symbol VVDDCOR
E
Parameter DC Supply Core DC Supply PLL DC Supply Peripheral I/Os Analog reference voltage Input Low-level Voltage
Condition
Min. 1.65 1.65 3.0 2.6 -0.3
Typ.
Max 1.95 1.95 3.6 3.6 +0.8 5.5V 3.6V 0.4
Units V V V V V V V V V
VVDDPLL VVDDIO VREF VIL VIH VOL VOH ILEAK
Input High-level Voltage
All GPIOS except for PC00, PC01, PC02, PC03, PC04, PC05. PC00, PC01, PC02, PC03, PC04, PC05.
2.0 2.0
Output Low-level Voltage Output High-level Voltage Input Leakage Current
IOL=-4mA IOL=4mA Pullup resistors disabled TQFP100 Package LQFP144 Package 10K 4 On VVDDCORE = 1.8V, CPU is in static mode All inputs driven; RESET_N=1, TA =25C TA =85C TA =25C TBD TBD 10 7 7 VVDDIO0.4
1
A pF pF Ohm mA A
CIN Input Capacitance RPULLUP IO Pull-up Resistance Output Current
ISC
Static Current
TBD
A A
ISCR
Static Current of internal regulator
Low Power mode (stop, deep stop or static
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12.3
12.3.1
Symbol VVDDIN VVDDOUT IOUT
Regulator characteristics
Electrical characteristics
Parameter Supply voltage (input) Supply voltage (output) Maximum DC output current with VVDDIN = 3.3V Maximum DC output current with VVDDIN = 2.7V Condition Min. 2.7 1.81 Typ. 3.3 1.85 Max. 3.6 1.89 100 90 Units V V mA mA
12.3.2
Symbol CIN1 CIN2 COUT1 COUT2
Decoupling requirements
Parameter Input Regulator Capacitor 1 Input Regulator Capacitor 2 Output Regulator Capacitor 1 Output Regulator Capacitor 2 Condition Typ. 1 4.7 470 2.2 Techno. NPO X7R NPO X7R Units nF uF pF uF
12.4
12.4.1
Analog characteristics
Electrical characteristics
Parameter Analog voltage reference (input) Condition Min. 2.6 Typ. Max. 3.6 Units V
Symbol VADVREF
12.4.2
Symbol CVREF1 CVREF2
Decoupling requirements
Parameter Voltage reference Capacitor 1 Voltage reference Capacitor 2 Condition Typ. 10 1 Techno. Units nF uF
12.4.3
BOD Table 12-1. BODLEVEL Values
Typ. Units.
BODLEVEL Value
000000b 010111b 011111b 100111b 111111b
1.58 1.62 1.67 1.77 1.92
V V V V V
The values in Table 12-1 describes the values of the BODLEVEL in the flash FGPFR register.
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12.5 Power Consumption
The values in Table 12-2 and Table 12-3 on page 43 are measured values of power consumption with operating conditions as follows: *VDDIO = 3.3V *VDDCORE = VDDPLL = 1.8V *TA = 25C, TA = 85C *I/Os are inactive Figure 12-1. Measurement setup
VDDANA
VDDIO
Amp0
VDDIN
Internal Voltage Regulator
VDDOUT
Amp1
VDDCORE
VDDPLL
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These figures represent the power consumption measured on the power supplies. Table 12-2. Power Consumption for Different Modes(1)
Consumption Typ. f = 12 MHz f = 24 MHz f = 36MHz f = 50 MHz 9 16 23 31.5
Mode
Conditions CPU running from flash. CPU clocked from PLL0 at f MHz Voltage regulator is on. XIN0 : external clock. (1) XIN1 stopped. XIN32 stopped PLL0 running All peripheral clocks activated. GPIOs on internal pull-up. JTAG unconnected with ext pull-up. Typ : Ta = 25 C CPU is in static mode GPIOs on internal pull-up. All peripheral clocks de-activated. DM and DP pins connected to ground. XIN0,Xin1 and XIN2 are stopped
Unit mA mA mA mA
Active
f = 60 MHz
37
mA
on Amp0
25
uA
Static
on Amp1
14
uA
1. Core frequency is generated from XIN0 using the PLL so that 140 MHz < fpll0 < 160 MHz and 10 MHz < fxin0 < 12MHz
Table 12-3.
Peripheral GPIO SMC SDRAMC ADC EBI INTC TWI MACB PDCA PWM RTC SPI SSC TC USART USB
Power Consumption by Peripheral in Active Mode
Consumption 37 10 4 18 31 25 14 45 A/MHz 30 36 7 13 13 10 35 45 Unit
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12.6 Clock Characteristics
These parameters are given in the following conditions: * VDDCORE = 1.8V * Ambient Temperature = 25C 12.6.1 CPU/HSB Clock Characteristics Core Clock Waveform Parameters
Parameter CPU Clock Frequency CPU Clock Period 15,15 Conditions Min Max 66 Units MHz ns
Table 12-4.
Symbol 1/(tCPCPU) tCPCPU
12.6.2
PBA Clock Characteristics PBA Clock Waveform Parameters
Parameter PBA Clock Frequency PBA Clock Period 15,15 Conditions Min Max 66 Units MHz ns
Table 12-5.
Symbol 1/(tCPPBA) tCPPBA
12.6.3
PBB Clock Characteristics PBB Clock Waveform Parameters
Parameter PBB Clock Frequency PBB Clock Period 15,15 Conditions Min Max 66 Units MHz ns
Table 12-6.
Symbol 1/(tCPPBB) tCPPBB
12.6.4
XIN Clock Characteristics XIN Clock Electrical Characteristics
Parameter XIN Clock Frequency Crystal XIN Clock High Half-period XIN Clock Low Half-period XIN Input Capacitance 3 0.4 x tCPXIN 0.4 x tCPXIN 20 0.6 x tCPXIN 0.6 x tCPXIN TBD pF MHz Conditions External clock Min Max 50 Units MHz
Table 12-7.
Symbol 1/(tCPXIN) tCHXIN tCLXIN CIN
12.7
Crystal Oscillator Characteristis
The following characteristics are applicable to the operating temperature range: TA = -40C to 85C and worst case of power supply, unless otherwise specified.
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12.7.1 32 KHz Oscillator Characteristics 32 KHz Oscillator Characteristics
Parameter Crystal Oscillator Frequency Duty Cycle CL tST IOSC Equivalent Load Capacitance Startup Time CL = 6pF CL = 12.5pF(1) Active mode Current Consumption Standby mode 1. CL is the equivalent load capacitance. 0.1 A
(1)
Table 12-8.
Symbol 1/(tCP32KHz)
Conditions
Min
Typ
Max 32 768
Unit Hz % pF ms A
40 6
50
60 12.5 600 1200 1.8
Note:
12.7.2
Main Oscillators Characteristics Main Oscillator Characteristics
Parameter Crystal Oscillator Frequency Internal Load Capacitance (CL1 = CL2) Equivalent Load Capacitance Duty Cycle 40 Conditions Min 0.45 12 TBD 50 60 TBD Active mode @TBD MHz TBD TBD Typ Max 16 Unit MHz pF pF % ms A A
Table 12-9.
Symbol 1/(tCPMAIN) CL1, CL2 CL
tST IOSC
Startup Time Current Consumption Standby mode @TBD V 1. CS is the shunt capacitance
Notes:
12.7.3
PLL Characteristics
Table 12-10. Phase Lock Loop Characteristics
Symbol FOUT FIN IPLL Parameter Output Frequency Input Frequency active mode Current Consumption standby mode TBD A Conditions Min 80 TBD Typ Max 240 TBD TBD Unit MHz MHz mA
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12.8 ADC Characteristics
Conditions 10-bit resolution mode 8-bit resolution mode Return from Idle Mode 600 ADC Clock = 5 MHz ADC Clock = 8 MHz ADC Clock = 5 MHz ADC Clock = 8 MHz 2 1.25 384(1) 533(2) Min Typ Max 5 8 20 Units MHz MHz s ns s s kSPS kSPS
Table 12-11. Channel Conversion Time and ADC Clock
Parameter ADC Clock Frequency ADC Clock Frequency Startup Time Track and Hold Acquisition Time Conversion Time Conversion Time Throughput Rate Throughput Rate Notes:
1. Corresponds to 13 clock cycles at 5 MHz: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion. 2. Corresponds to 15 clock cycles at 8 MHz: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
Table 12-12. External Voltage Reference Input
Parameter ADVREF Input Voltage Range ADVREF Average Current Current Consumption on VDDANA On 13 samples with ADC Clock = 5 MHz Conditions Min 2.6 200 Typ Max VDDANA 250 TBD Units V A mA
Table 12-13. Analog Inputs
Parameter Input Voltage Range Input Leakage Current Input Capacitance Min 0 TBD 17 Typ Max VADVREF A pF Units
Table 12-14. Transfer Characteristics
Parameter Resolution Absolute Accuracy Integral Non-linearity Differential Non-linearity Offset Error Gain Error f=5MHz f=5MHz f=5MHz f=5MHz f=5MHz -0.5 -0.5 0.35 0.3 Conditions Min Typ 10 0.8 0.5 0.5 0.5 0.5 Max Units Bit LSB LSB LSB LSB LSB
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12.9 EBI Timings
These timings are given for worst case process, T = 85C, VDDCORE = 1.65V, VDDIO = 3V and 40 pF load capacitance.
Table 12-15. SMC Clock Signal.
Symbol 1/(tCPSMC) Note: Parameter SMC Controller Clock Frequency Max(1) 1/(tcpcpu) Units MHz
1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Table 12-16. SMC Read Signals with Hold Settings
Symbol Parameter NRD Controlled (READ_MODE = 1) SMC1 SMC2 SMC3 SMC4 SMC5 SMC6 SMC7 SMC8 SMC9 Min Units
Data Setup before NRD High Data Hold after NRD High NRD High to NBS0/A0 Change NRD High to NBS1 Change(1) NRD High to NBS2/A1 Change NRD High to NBS3 Change(1) NRD High to A2 - A25 Change NRD High to NCS Inactive(1) NRD Pulse Width
(1) (1) (1)
12 0
nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 nrd hold length * tCPSMC - 1.3 (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 nrd pulse length * tCPSMC - 1.4
ns
NRD Controlled (READ_MODE = 0) SMC10 SMC11 SMC12 SMC13 SMC14 SMC15 SMC16 SMC17 SMC18 Note:
Data Setup before NCS High Data Hold after NCS High NCS High to NBS0/A0 Change
(1)
11.5 0
ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 2.3 ncs rd hold length * tCPSMC - 4 ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ncs rd pulse length * tCPSMC - 3.6
ns
NCS High to NBS0/A0 Change(1) NCS High to NBS2/A1 Change NCS High to NBS3 Change(1) NCS High to A2 - A25 Change NCS High to NRD Inactive(1) NCS Pulse Width
(1) (1)
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs rd hold length" or "nrd hold length".
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Table 12-17. SMC Read Signals with no Hold Settings
Symbol Parameter NRD Controlled (READ_MODE = 1) SMC19 SMC20 Min Units
Data Setup before NRD High Data Hold after NRD High
NRD Controlled (READ_MODE = 0)
13.7 ns 1
SMC21 SMC22
Data Setup before NCS High Data Hold after NCS High
13.3 ns 0
Table 12-18. SMC Write Signals with Hold Settings
Symbol Parameter NRD Controlled (READ_MODE = 1) SMC23 SMC24 SMC25 SMC26 SMC29 SMC30 SMC31 SMC32 SMC33 Min Units
Data Out Valid before NWE High Data Out Valid after NWE High(1) NWE High to NBS0/A0 Change NWE High to NBS1 Change(1) NWE High to NBS2/A1 Change NWE High to NBS3 Change(1) NWE High to A2 - A25 Change NWE High to NCS Inactive(1) NWE Pulse Width
(1) (1) (1)
(nwe pulse length - 1) * tCPSMC - 0.9 nwe hold length * tCPSMC - 6 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.9 nwe hold length * tCPSMC - 1.7 (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 nwe pulse length * tCPSMC - 0.9
ns
NRD Controlled (READ_MODE = 0) SMC34 SMC35 SMC36 Note:
Data Out Valid before NCS High Data Out Valid after NCS High(1) NCS High to NWE Inactive
(1)
(ncs wr pulse length - 1)* tCPSMC - 4.6 ncs wr hold length * tCPSMC - 5.8 (ncs wr hold length - nwe hold length)* tCPSMC - 0.6
ns
1. hold length = total cycle duration - setup duration - pulse duration. "hold length" is for "ncs wr hold length" or "nwe hold length"
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Table 12-19. SMC Write Signals with No Hold Settings (NWE Controlled only).
Symbol SMC37 SMC38 SMC39 SMC40 SMC41 SMC42 SMC43 SMC44 SMC45 Parameter Min Units
NWE Rising to A2-A25 Valid NWE Rising to NBS0/A0 Valid NWE Rising to NBS1 Change NWE Rising to A1/NBS2 Change NWE Rising to NBS3 Change NWE Rising to NCS Rising Data Out Valid before NWE Rising Data Out Valid after NWE Rising NWE Pulse Width
5.4 5 5 5 5 5.1 (nwe pulse length - 1) * tCPSMC - 1.2 5 nwe pulse length * tCPSMC - 0.9
ns
Figure 12-2. SMC Signals for NCS Controlled Accesses.
SMC16 SMC16 SMC16
A2-A25
SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15 SMC12 SMC13 SMC14 SMC15
A0/A1/NBS[3:0]
NRD
SMC17 SMC17
NCS
SMC18 SMC22
SMC18
SMC18
SMC21
SMC10
SMC11
SMC34
SMC35
D0 - D15
SMC36
NWE
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Figure 12-3. SMC Signals for NRD and NRW Controlled Accesses.
SMC7 SMC37 SMC7 SMC31
A2-A25
SMC3 SMC4 SMC5 SMC6 SMC38 SMC39 SMC40 SMC41 SMC3 SMC4 SMC5 SMC6 SMC25 SMC26 SMC29 SMC30
A0/A1/NBS[3:0]
SMC42 SMC8 SMC32
NCS
SMC8
NRD
SMC9
SMC9
SMC19
SMC20
SMC43
SMC44
SMC1
SMC2
SMC23
SMC24
D0 - D15
SMC45
SMC33
NWE
12.9.1
SDRAM Signals These timings are given for 10 pF load on SDCK and 40 pF on other signals. Table 12-20. SDRAM Clock Signal.
Symbol 1/(tCPSDCK) Note: Parameter SDRAM Controller Clock Frequency Max(1) 1/(tcpcpu) Units MHz
1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
Table 12-21. SDRAM Clock Signal.
Symbol SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4 SDRAMC5 SDRAMC6 SDRAMC7 SDRAMC8 SDRAMC9 SDRAMC10 Parameter Min 7.4 3.2 7 2.9 7.5 1.6 7.2 2.3 7.6 1.9 Units ns
SDCKE High before SDCK Rising Edge SDCKE Low after SDCK Rising Edge SDCKE Low before SDCK Rising Edge SDCKE High after SDCK Rising Edge SDCS Low before SDCK Rising Edge SDCS High after SDCK Rising Edge RAS Low before SDCK Rising Edge RAS High after SDCK Rising Edge SDA10 Change before SDCK Rising Edge SDA10 Change after SDCK Rising Edge
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Table 12-21. SDRAM Clock Signal.
Symbol SDRAMC11 SDRAMC12 SDRAMC13 SDRAMC14 SDRAMC15 SDRAMC16 SDRAMC17 SDRAMC18 SDRAMC19 SDRAMC20 SDRAMC23 SDRAMC24 SDRAMC25 SDRAMC26 Parameter Min 6.2 2.2 6.3 2.4 7.4 1.9 6.4 ns 2.2 9 0 7.6 1.8 7.1 1.5 Units
Address Change before SDCK Rising Edge Address Change after SDCK Rising Edge Bank Change before SDCK Rising Edge Bank Change after SDCK Rising Edge CAS Low before SDCK Rising Edge CAS High after SDCK Rising Edge DQM Change before SDCK Rising Edge DQM Change after SDCK Rising Edge D0-D15 in Setup before SDCK Rising Edge D0-D15 in Hold after SDCK Rising Edge SDWE Low before SDCK Rising Edge SDWE High after SDCK Rising Edge D0-D15 Out Valid before SDCK Rising Edge D0-D15 Out Valid after SDCK Rising Edge
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Figure 12-4. SDRAMC Signals relative to SDCK.
SDCK
SDRAMC1 SDRAMC2 SDRAMC3 SDRAMC4
SDCKE
SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6 SDRAMC5 SDRAMC6
SDCS
SDRAMC7 SDRAMC8
RAS
SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16
CAS
SDRAMC23 SDRAMC24
SDWE
SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10 SDRAMC9 SDRAMC10
SDA10
SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12
A0 - A9, A11 - A13
SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14
BA0/BA1
SDRAMC17 SDRAMC18 SDRAMC17 SDRAMC18
DQM0 DQM3
SDRAMC19 SDRAMC20
D0 - D15 Read
SDRAMC25 SDRAMC26
D0 - D15 to Write
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12.10 JTAG Timings
12.10.1 JTAG Interface Signals
Table 12-22. JTAG Interface Timing specification
Symbol JTAG0 JTAG1 JTAG2 JTAG3 JTAG4 JTAG5 JTAG6 JTAG7 JTAG8 JTAG9 JTAG10 Note: Parameter TCK Low Half-period TCK High Half-period TCK Period TDI, TMS Setup before TCK High TDI, TMS Hold after TCK High TDO Hold Time TCK Low to TDO Valid Device Inputs Setup Time Device Inputs Hold Time Device Outputs Hold Time TCK to Device Outputs Valid 1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF Conditions
(1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1)
Min 6 3 9 1 0 4
Max
Units ns ns ns ns ns ns
6
ns ns ns ns ns
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Figure 12-5. JTAG Interface Signals
JTAG2 TCK JTAG JTAG1
0
TMS/TDI JTAG3 JTAG4
TDO JTAG5 JTAG6 Device Inputs JTAG7 JTAG8
Device Outputs JTAG9 JTAG10
12.11 SPI Characteristics
Figure 12-6. SPI Master mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI0 MISO
SPI1
SPI2 MOSI
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Figure 12-7. SPI Master mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI3 MISO
SPI4
SPI5 MOSI
Figure 12-8. SPI Slave mode with (CPOL=0 and NCPHA=1) or (CPOL=1 and NCPHA=0)
SPCK
SPI6 MISO
SPI7 MOSI
SPI8
Figure 12-9. SPI Slave mode with (CPOL = NCPHA = 0) or (CPOL= NCPHA= 1)
SPCK
SPI9 MISO
SPI10 MOSI
SPI11
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Table 12-23. SPI Timings
Symbol SPI0 SPI1 SPI2 SPI3 SPI4 SPI5 SPI6 SPI7 SPI8 SPI9 SPI10 SPI11 Notes: Parameter MISO Setup time before SPCK rises (master) MISO Hold time after SPCK rises (master) SPCK rising to MOSI Delay (master) MISO Setup time before SPCK falls (master) MISO Hold time after SPCK falls (master) SPCK falling to MOSI Delay (master) SPCK falling to MISO Delay (slave) MOSI Setup time before SPCK rises (slave) MOSI Hold time after SPCK rises (slave) SPCK rising to MISO Delay (slave) MOSI Setup time before SPCK falls (slave) MOSI Hold time after SPCK falls (slave) Conditions 3.3V domain 3.3V domain 3.3V domain 3.3V domain
(1) (1) (1) (1)
Min 22 + (tCPMCK)/2 0
(2)
Max
Units ns ns
7 22 + (tCPMCK)/2 0 7 26.5 0 1.5 27 0 1
(2)
ns ns ns ns ns ns ns ns ns ns
3.3V domain (1) 3.3V domain (1) 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain 3.3V domain
(1) (1) (1) (1) (1) (1)
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF. 2. tCPMCK: Master Clock period in ns.
12.12 MACB Characteristics
Table 12-24. Ethernet MAC Signals
Symbol EMAC1 EMAC2 EMAC3 Notes: Parameter Setup for EMDIO from EMDC rising Hold for EMDIO from EMDC rising EMDIO toggling from EMDC falling 1. f: MCK frequency (MHz) 2. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF Conditions Load: 20pF
(2)
Min (ns)
Max (ns)
Load: 20pF(2) Load: 20pF(2)
Table 12-25. Ethernet MAC MII Specific Signals
Symbol EMAC4 EMAC5 EMAC6 EMAC7 EMAC8 EMAC9 EMAC10 EMAC11 Parameter Setup for ECOL from ETXCK rising Hold for ECOL from ETXCK rising Setup for ECRS from ETXCK rising Hold for ECRS from ETXCK rising ETXER toggling from ETXCK rising ETXEN toggling from ETXCK rising ETX toggling from ETXCK rising Setup for ERX from ERXCK Conditions Load: 20pF Load: 20pF Load: 20pF
(1) (1) (1)
Min (ns) 3 0 3 0
Max (ns)
Load: 20pF (1) Load: 20pF Load: 20pF Load: 20pF
(1) (1) (1)
15 15 15 1
Load: 20pF (1)
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Table 12-25. Ethernet MAC MII Specific Signals
Symbol EMAC12 EMAC13 EMAC14 EMAC15 EMAC16 Note: Parameter Hold for ERX from ERXCK Setup for ERXER from ERXCK Hold for ERXER from ERXCK Setup for ERXDV from ERXCK Hold for ERXDV from ERXCK Conditions Load: 20pF Load: 20pF Load: 20pF
(1) (1) (1)
Min (ns) 1.5 1 0.5 1.5 1
Max (ns)
Load: 20pF (1) Load: 20pF (1)
1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 20 pF
Figure 12-10. Ethernet MAC MII Mode
EMDC EMAC1 EMDIO EMAC4 ECOL EMAC6 ECRS EMAC7 EMAC5 EMAC2 EMAC3
ETXCK EMAC8 ETXER EMAC9 ETXEN EMAC10 ETX[3:0]
ERXCK EMAC11 ERX[3:0] EMAC13 ERXER EMAC15 ERXDV EMAC16 EMAC14 EMAC12
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Table 12-26. Ethernet MAC RMII Specific Signals
Symbol EMAC21 EMAC22 EMAC23 EMAC24 EMAC25 EMAC26 EMAC27 EMAC28 Parameter ETXEN toggling from EREFCK rising ETX toggling from EREFCK rising Setup for ERX from EREFCK Hold for ERX from EREFCK Setup for ERXER from EREFCK Hold for ERXER from EREFCK Setup for ECRSDV from EREFCK Hold for ECRSDV from EREFCK Min (ns) 7 7 1.5 0 1.5 0 1.5 0 Max (ns) 14.5 14.7
Figure 12-11. Ethernet MAC RMII Mode
EREFCK EMAC21 ETXEN EMAC22 ETX[1:0] EMAC23 ERX[1:0] EMAC25 ERXER EMAC27 ECRSDV EMAC28 EMAC26 EMAC24
12.13 Flash Characteristics
The following table gives the device maximum operating frequency depending on the field FWS of the Flash FSR register. This field defines the number of wait states required to access the Flash Memory.
Table 12-27.
Flash Wait States
FWS 0 1 Read Operations 1 cycle 2 cycles Maximum Operating Frequency (MHz) 33 66
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13. Mechanical Characteristics
13.1
13.1.1
Thermal Considerations
Thermal Data Table 13-1 summarizes the thermal resistance data depending on the package. Table 13-1.
Symbol JA JC JA JC
Thermal Resistance Data
Parameter Junction-to-ambient thermal resistance Junction-to-case thermal resistance Junction-to-ambient thermal resistance Junction-to-case thermal resistance Still Air Condition Still Air Package TQFP100 TQFP100 LQFP144 LQFP144 Typ TBD TBD TBD TBD C/W Unit C/W
13.1.2
Junction Temperature The average chip-junction temperature, TJ, in C can be obtained from the following: 1. 2. T J = T A + ( P D x JA )
T J = T A + ( P D x ( HEATSINK + JC ) )
where: * JA = package thermal resistance, Junction-to-ambient (C/W), provided in Table 13-1 on page 59. * JC = package thermal resistance, Junction-to-case thermal resistance (C/W), provided in Table 13-1 on page 59. * HEAT SINK = cooling device thermal resistance (C/W), provided in the device datasheet. * PD = device power consumption (W) estimated from data provided in the section "Power Consumption" on page 42. * TA = ambient temperature (C). From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average chip-junction temperature TJ in C.
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13.2 Package Drawings
Figure 13-1. TQFP-100 package drawing
Table 13-2.
TBD
Device and Package Maximum Weight
mg
Table 13-3.
Package Characteristics
TBD
Moisture Sensitivity Level
Table 13-4.
Package Reference
MS-026 E3
JEDEC Drawing Reference JESD97 Classification
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Figure 13-2. LQFP-144 package drawing
Table 13-5.
TBD
Device and Package Maximum Weight
mg
Table 13-6.
Package Characteristics
TBD
Moisture Sensitivity Level
Table 13-7.
Package Reference
MS-026 E3
JEDEC Drawing Reference JESD97 Classification
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13.3 Soldering Profile
Table 13-8 gives the recommended soldering profile from J-STD-20. Table 13-8. Soldering Profile
Green Package TBD TBD TBD TBD TBD TBD TBD
Profile Feature Average Ramp-up Rate (217C to Peak) Preheat Temperature 175C 25C Temperature Maintained Above 217C Time within 5C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25C to Peak Temperature Note:
It is recommended to apply a soldering temperature higher than 250C.
A maximum of three reflow passes is allowed per component.
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14. Ordering Information
Table 14-1.
Device AT32UC3A0512
Ordering Information
Ordering Code AT32UC3A0512-ALUT AT32UC3A0512-ALUR AT32UC3A0512-ALTR AT32UC3A0512-ALTT AT32UC3A0512-ALTES Package 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 144 lead LQFP 100 lead TQFP 100 lead TQFP 100 lead TQFP 100 lead TQFP 100 lead TQFP 100 lead TQFP Conditioning Tray Reel Reel Tray Tray Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Temperature Operating Range Industrial (-40C to 85C) Industrial (-40C to 85C) Automotive (-40C to 85C) Automotive (-40C to 85C) Automotive (-40C to 85C) samples Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C) Industrial (-40C to 85C)
AT32UC3A0256 AT32UC3A0128 AT32UC3A1512 AT32UC3A1256 AT32UC3A1128
AT32UC3A0256-ALUT AT32UC3A0256-ALUR AT32UC3A0128-ALUT AT32UC3A0128-ALUR AT32UC3A1512-AUT AT32UC3A1512-AUR AT32UC3A1256-AUT AT32UC3A1256-AUR AT32UC3A1128-AUT AT32UC3A1128-AUR
14.1
Automotive Quality Grade
The AT32UC3A have been developed and manufactured according to the most stringent requirements of the international standard ISO-TS-16949. This data sheet will contain limit values extracted from the results of extensive characterization (Temperature and Voltage). The quality and reliability of the AT32UC3A is verified during regular product qualification as per AEC-Q100 grade 3. As indicated in the ordering information paragraph, the product is available in only one temperature grade T: -40C / + 85C.
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15. Errata
All industrial parts labelled with -UES (engineering samples) are revision E parts.
15.1
15.1.1
Rev. J
PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 3. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0.
15.1.2
ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion.
15.1.3
SPI 1. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 2. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1.
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3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected. 5. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 15.1.4 Power Manager 1. If the BOD level is higher than VDDCORE, the part is constantly under reset If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. Fix/Workaround Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than VDDCORE max and disable the BOD. 15.1.5 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID. Fix/Workaround The same PID should not be assigned to more than one channel. 15.1.6 TWI 1. The TWI RXRDY flag in SR register is not reset when a software reset is performed. Fix/Workaround After a Software Reset, the register TWI RHR must be read. 15.1.7 SDRAMC 1. Code execution from external SDRAM does not work Code execution from SDRAM does not work. Fix/Workaround Do not run code from SDRAM.
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15.1.8 Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE.
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15.2
15.2.1
Rev. I
PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 3. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0.
15.2.2
ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion.
15.2.3
SPI 1. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 2. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 3. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround
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AT32UC3A
When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected. 5. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. 15.2.4 Power Manager 1. If the BOD level is higher than VDDCORE, the part is constantly under reset If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. Fix/Workaround Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than VDDCORE max and disable the BOD. 15.2.5 Flashc 1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen - After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading (data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or through the EBI. After these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.2.6 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID.
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Workaround/fix The same PID should not be assigned to more than one channel. 15.2.7 GPIO 1. Some GPIO VIH (input high voltage) are 3.6V max instead of 5V tolerant Only 11 GPIOs remain 5V tolerant (VIHmax=5V): PB01, PB02, PB03, PB10, PB19, PB20, PB21, PB22, PB23, PB27, PB28. Workaround/fix None. 15.2.8 TWI 1. The TWI RXRDY flag in SR register is not reset when a software reset is performed. Fix/Workaround After a Software Reset, the register TWI RHR must be read. 15.2.9 SDRAMC 1. Code execution from external SDRAM does not work Code execution from SDRAM does not work.
15.2.10
Fix/Workaround Do not run code from SDRAM. Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE.
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AT32UC3A
15.3
15.3.1
Rev. H
PWM 1. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 2. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 3. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0.
15.3.2
ADC 1. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion.
15.3.3
SPI 1. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 2. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1 3. SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a Software Reset.
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AT32UC3A
4. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK. Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 5. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected. 6. SPI Disable does not work in Slave mode Fix/workaround Read the last received data then perform a Software reset. Power Manager 1. Wrong reset causes when BOD is activated Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the reset source even though the part was reset by another source. Fix/Workaround Do not set the BOD enable fuse, but activate the BOD as soon as your program starts. 2. If the BOD level is higher than VDDCORE, the part is constantly under reset If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. Fix/Workaround Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than VDDCORE max and disable the BOD. 15.3.5 FLASHC 1. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen - After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading
15.3.4
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(data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or through the EBI. After these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.3.6 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID. Workaround/fix The same PID should not be assigned to more than one channel. 15.3.7 TWI 1. The TWI RXRDY flag in SR register is not reset when a software reset is performed. Fix/Workaround After a Software Reset, the register TWI RHR must be read. 15.3.8 SDRAMC 1. Code execution from external SDRAM does not work Code execution from SDRAM does not work.
15.3.9
Fix/Workaround Do not run code from SDRAM. Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE.
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15.4
15.4.1
Rev. E
SPI 1. SPI FDIV option does not work Selecting clock signal using FDIV = 1 does not work as specified. Fix/Workaround Do not set FDIV = 1. 2. SPI Slave / PDCA transfer: no TX UNDERRUN flag There is no TX UNDERRUN flag available, therefore in SPI slave mode, there is no way to be informed of a character lost in transmission. Fix/Workaround For PDCA transfer: none. 3. SPI Bad serial clock generation on 2nd chip select when SCBR=1, CPOL=1 and CNCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrate equals to 1, the other must also equal 1 if CPOL=1 and CPHA=0. 4. SPI Glitch on RXREADY flag in slave mode when enabling the SPI or during the first transfer In slave mode, the SPI can generate a false RXREADY signal during enabling of the SPI or during the first transfer. Fix/Workaround 1. Set slave mode, set required CPOL/CPHA. 2. Enable SPI. 3. Set the polarity CPOL of the line in the opposite value of the required one. 4. Set the polarity CPOL to the required one. 5. Read the RXHOLDING register. Transfers can now befin and RXREADY will now behave as expected. 5. SPI CSNAAT bit 2 in register CSR0...CSR3 is not available. Fix/Workaround Do not use this bit. 6. SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a Software Reset. 7. SPI Bad Serial Clock Generation on 2nd chip_select when SCBR = 1, CPOL=1 and NCPHA=0 When multiple CS are in use, if one of the baudrate equals to 1 and one of the others doesn't equal to 1, and CPOL=1 and CPHA=0, then an aditional pulse will be generated on SCK.
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Fix/workaround When multiple CS are in use, if one of the baudrate equals 1, the other must also equal 1 if CPOL=1 and CPHA=0. 15.4.2 PWM 1. PWM counter restarts at 0x0001 The PWM counter restarts at 0x0001 and not 0x0000 as specified. Because of this the first PWM period has one more clock cycle. Fix/Workaround - The first period is 0x0000, 0x0001, ..., period - Consecutive periods are 0x0001, 0x0002, ..., period 2. PWM channel interrupt enabling triggers an interrupt When enabling a PWM channel that is configured with center aligned period (CALG=1), an interrupt is signalled. Fix/Workaround When using center aligned mode, enable the channel and read the status before channel interrupt is enabled. 3. PWM update period to a 0 value does not work It is impossible to update a period equal to 0 by the using the PWM update register (PWM_CUPD). Fix/Workaround Do not update the PWM_CUPD register with a value equal to 0. 4. PWM channel status may be wrong if disabled before a period has elapsed Before a PWM period has elapsed, the read channel status may be wrong. The CHIDx-bit for a PWM channel in the PWM Enable Register will read '1' for one full PWM period even if the channel was disabled before the period elapsed. It will then read '0' as expected. Fix/Workaround Reading the PWM channel status of a disabled channel is only correct after a PWM period has elapsed. 15.4.3 SSC 1. SSC does not trigger RF when data is low The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or RCMR respectively. Fix/Workaround Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO. 2. SSC Data is not sent unless clock is set as output The SSC cannot transmit or receive data when CKS = CKDIV and CKO = none, in TCMR or RCMR respectively. Fix/Workaround Set CKO to a value that is not "none" and bypass the output of the TK/RK pin with the PIO.
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15.4.4 USB 1. USB No end of host reset signaled upon disconnection In host mode, in case of an unexpected device disconnection whereas a usb reset is being sent by the usb controller, the UHCON.RESET bit may not been cleared by the hardware at the end of the reset. Fix/Workaround A software workaround consists in testing (by polling or interrupt) the disconnection (UHINT.DDISCI == 1) while waiting for the end of reset (UHCON.RESET == 0) to avoid being stuck. 2. USBFSM and UHADDR1/2/3 registers are not available. Do not use USBFSM register. Fix/Workaround Do not use USBFSM register and use HCON[6:0] field instead for all the pipes. 15.4.5 Processor and Architecture 1. Incorrect Processor ID The processor ID reads 0x01 and not 0x02 as it should. Fix/Workaround None. 2. Bus error should be masked in Debug mode If a bus error occurs during debug mode, the processor will not respond to debug commands through the DINST register. Fix/Workaround A reset of the device will make the CPU respond to debug commands again. 3. Read Modify Write (RMW) instructions on data outside the internal RAM does not work. Read Modify Write (RMW) instructions on data outside the internal RAM does not work. Fix/Workaround Do not perform RMW instructions on data outside the internal RAM. 4. CRC calculation of a locked device will calculate CRC for 512 kB of flash memory, even though the part has less flash. Fix/Workaround The flash address space is wrapping, so it is possible to use the CRC value by calculating CRC of the flash content concatenated with itself N times. Where N is 512 kB/flash size. Need two NOPs instruction after instructions masking interrupts The instructions following in the pipeline the instruction masking the interrupt through SR may behave abnormally. Fix/Workaround Place two NOPs instructions after each SSRF or MTSR instruction setting IxM or GM in SR.
5.
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6. CPU Cycle Counter does not reset the COUNT system register on COMPARE match. The device revision E does not reset the COUNT system register on COMPARE match. In this revision, the COUNT register is clocked by the CPU clock, so when the CPU clock stops, so does incrementing of COUNT. Fix/Workaround None. 7. Memory Protection Unit (MPU) is non functional. Fix/Workaround Do not use the MPU. 8. The following alternate GPIO function C are not available in revE MACB-WOL on GPIO9 (PA09), MACB-WOL on GPIO18 (PA18), USB-USB_ID on GPIO21 (PA21), USB-USB_VBOF on GPIO22 (PA22), and all function B and C on GPIO70 to GPIO101 (PX00 to PX39). Fix/Workaround Do not use these alternate B and C functions on the listed GPIO pins. 9. Clock connection table on Rev E Here is the table of Rev E Figure 15-1. Timer/Counter clock connections on RevE
Source Internal Name TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 External XC0 XC1 XC2 Connection 32 KHz Oscillator PBA Clock / 4 PBA Clock / 8 PBA Clock / 16 PBA Clock / 32
10. Local Bus fast GPIO not available in RevE. Fix/Workaround Do not use on this silicon revision. 11. Spurious interrupt may corrupt core SR mode to exception If the rules listed in the chapter Masking interrupt requests in peripheral modules' of the AVR32UC Technical Reference Manual are not followed, a spurious interrupt may occur. An interrupt context will be pushed onto the stack while the core SR mode will indicate an exception. A RETE instruction would then corrupt the stack.. Fix/Workaround Follow the rules of the AVR32UC Technical Reference Manual. To increase software robustness, if an exception mode is detected at the beginning of an interrupt handler, change the stack interrupt context to an exception context and issue a RETE instruction.
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12. CPU cannot operate on a divided slow clock (internal RC oscillator) Fix/Workaround Do not run the CPU on a divided slow clock. 15.4.6 SDRAMC 1. Code execution from external SDRAM does not work Code execution from SDRAM does not work. Fix/Workaround Do not run code from SDRAM. 2. SDRAM SDCKE rise at the same time as SDCK while exiting self-refresh mode SDCKE rise at the same time as SDCK while exiting self-refresh mode. Fix/Workaround None. 15.4.7 USART 1. USART Manchester Encoder Not Working Manchester encoding/decoding is not working. Fix/Workaround Do not use manchester encoding. 2. USART RXBREAK problem when no timeguard In asynchronous mode the RXBREAK flag is not correctly handled when the timeguard is 0 and the break character is located just after the stop bit. Fix/Workaround If the NBSTOP is 1, timeguard should be different from 0. 3. USART Handshaking: 2 characters sent / CTS rises when TX If CTS switches from 0 to 1 during the TX of a character, if the Holding register is not empty, the TXHOLDING is also transmitted. Fix/Workaround None. 4. USART PDC and TIMEGUARD not supported in MANCHESTER Manchester encoding/decoding is not working. Fix/Workaround Do not use manchester encoding. 5. USART SPI mode is non functional on this revision. Fix/Workaround Do not use the USART SPI mode. 6. DCD is active High instead of Low. In modem mode the DCD signal is assumed to be active high by the USART, butshould have been active low. Fix/Workaround
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Add an external inverter to the DCD line. 15.4.8 Power Manager 1. Voltage regulator input and output is connected to VDDIO and VDDCORE inside the device The voltage regulator input and output is connected to VDDIO and VDDCORE respectively inside the device. Fix/Workaround Do not supply VDDCORE externally, as this supply will work in paralell with the regulator. 2. Wrong reset causes when BOD is activated Setting the BOD enable fuse will cause the Reset Cause Register to list BOD reset as the reset source even though the part was reset by another source. Fix/Workaround Do not set the BOD enable fuse, but activate the BOD as soon as your program starts. 3. PLL0/1 Lock control does not work Lock Control does not work for PLL0 and PLL1. Fix/Workaround In PLL0/1 Control register, the bit 7 should be set in order to prevent unexpected behaviour. 4. Peripheral Bus A maximum frequency is 33MHz instead of 66MHz. Fix/Workaround Do not set PBA frequency higher than 33 MHz. 5. PCx pins go low in stop mode In sleep mode stop all PCx pins will be controlled by GPIO module instead of oscillators. This can cause drive contention on the XINx in worst case. Fix/Workaround Before entering stop mode set all PCx pins to input and GPIO controlled. 6. On some rare parts, the maximum HSB and CPU speed is 50MHz instead of 66MHz. Fix/Workaround Do not set the HSB/CPU speed higher than 50MHz when the firmware generate exceptions.
7. If the BOD level is higher than VDDCORE, the part is constantly under reset If the BOD level is set to a value higher than VDDCORE and enabled by fuses, the part will be in constant reset. Fix/Workaround Apply an external voltage on VDDCORE that is higher than the BOD level and is lower than VDDCORE max and disable the BOD. 8. System Timer mask (Bit 16) of the PM CPUMASK register is not available. Fix/Workaround Do not use this bit.
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15.4.9 HMatrix 1. HMatrix fixed priority arbitration does not work Fixed priority arbitration does not work. Fix/Workaround Use Round-Robin arbitration instead. 15.4.10 ADC 1. ADC possible miss on DRDY when disabling a channel The ADC does not work properly when more than one channel is enabled. Fix/Workaround Do not use the ADC with more than one channel enabled at a time. 2. ADC OVRE flag sometimes not reset on Status Register read The OVRE flag does not clear properly if read simultaneously to an end of conversion. Fix/Workaround None. 3. Sleep Mode activation needs additional A to D conversion If the ADC sleep mode is activated when the ADC is idle the ADC will not enter sleep mode before after the next AD conversion. Fix/Workaround Activate the sleep mode in the mode register and then perform an AD conversion. 15.4.11 ABDAC 1. Audio Bitstream DAC is not functional. Fix/Workaround Do not use the ABDAC on revE. 15.4.12 FLASHC 1. The address of Flash General Purpose Fuse Register Low (FGPFRLO) is 0xFFFE140C on revE instead of 0xFFFE1410. Fix/Workaround None. 2. The command Quick Page Read User Page(QPRUP) is not functional. Fix/Workaround None. 3. PAGEN Semantic Field for Program GP Fuse Byte is WriteData[7:0], ByteAddress[1:0] on revision E instead of WriteData[7:0], ByteAddress[2:0]. Fix/Workaround None. 4. On AT32UC3A0512 and AT32UC3A1512, corrupted read in flash after FLASHC WP, EP, EA, WUP, EUP commands may happen
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- After a FLASHC Write Page (WP) or Erase Page (EP) command applied to a page in a given half of the flash (first or last 256 kB of flash), reading (data read or code fetch) the other half of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Erase All (EA) command, reading (data read or code fetch) the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. - After a FLASHC Write User Page (WUP) or Erase User Page (EUP) command, reading (data read or code fetch) the second half (last 256 kB) of the flash may fail. This may lead to an exception or to other errors derived from this corrupted read access. Fix/Workaround Flashc WP, EP, EA, WUP, EUP commands: these commands must be issued from RAM or through the EBI. After these commands, read twice one flash page initialized to 00h in each half part of the flash. 15.4.13 RTC 1. Writes to control (CTRL), top (TOP) and value (VAL) in the RTC are discarded if the RTC peripheral bus clock (PBA) is divided by a factor of four or more relative to the HSB clock. Fix/Workaround Do not write to the RTC registers using the peripheral bus clock (PBA) divided by a factor of four or more relative to the HSB clock. 2. The RTC CLKEN bit (bit number 16) of CTRL register is not available. Fix/Workaround Do not use the CLKEN bit of the RTC on Rev E. 15.4.14 OCD 1. Stalled memory access instruction writeback fails if followed by a HW breakpoint. Consider the following assembly code sequence: A B If a hardware breakpoint is placed on instruction B, and instruction A is a memory access instruction, register file updates from instruction A can be discarded. Fix/Workaround Do not place hardware breakpoints, use software breakpoints instead. Alternatively, place a hardware breakpoint on the instruction before the memory access instruction and then single step over the memory access instruction. 15.4.15 PDCA 1. Wrong PDCA behavior when using two PDCA channels with the same PID. Workaround/fix The same PID should not be assigned to more than one channel. 15.4.16 TWI 1. The TWI RXRDY flag in SR register is not reset when a software reset is performed. Fix/Workaround After a Software Reset, the register TWI RHR must be read. Processor and Architecture 1. LDM instruction with PC in the register list and without ++ increments Rp
15.4.17
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For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the increment of the pointer is done in parallel with the testing of R12. Fix/Workaround None. 2. RETE instruction does not clear SREG[L] from interrupts. The RETE instruction clears SREG[L] as expected from exceptions. Fix/Workaround When using the STCOND instruction, clear SREG[L] in the stacked value of SR before returning from interrupts with RETE.
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16. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision.
16.1
Rev. F - 08/08
1. 2.
Add revision J to "Errata" on page 64. Update DMIPS number in "Features" on page 1.
16.2
Rev. E - 04/08
1.
Open Drain Mode removed from "General-Purpose Input/Output Controller (GPIO)" on page 151.
16.3
Rev. D - 04/08
1. 2.
Updated "Signal Description List" on page 8. Removed RXDN and TXDN from USART section. Updated "Errata" on page 64. Rev G replaced by rev H.
16.4
Rev. C - 10/07
1. 2.
Updated "Signal Description List" on page 8. Removed RXDN and TXDN from USART section. Updated "Errata" on page 64. Rev G replaced by rev H.
16.5
Rev. B - 10/07
1. 2. 3. 4.
Updated "Features" on page 1. Update "Blockdiagram" on page 4 with local bus. Updated "Peripherals" on page 34 with local bus. Add SPI feature in "Universial Synchronous/Asynchronous Receiver/Transmitter (USART)" on page 315.
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5. 6. 7.
Updated "USB On-The-Go Interface (USBB)" on page 517. Updated "JTAG and Boundary Scan" on page 750 with programming procedure . Add description for silicon Rev G.
16.6
Rev. A - 03/07
1.
Initial revision.
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Table of Contents
1 2 3 4 Description ............................................................................................... 3 Configuration Summary .......................................................................... 4 Abbreviations ........................................................................................... 4 Blockdiagram ........................................................................................... 5
4.1Processor and architecture .......................................................................................6
5 6 7
Signals Description ................................................................................. 8 Package and Pinout ............................................................................... 13 Power Considerations ........................................................................... 16
7.1Power Supplies .......................................................................................................16 7.2Voltage Regulator ....................................................................................................17 7.3Analog-to-Digital Converter (A.D.C) reference. .......................................................18
8
I/O Line Considerations ......................................................................... 19
8.1JTAG pins ................................................................................................................19 8.2RESET_N pin ..........................................................................................................19 8.3TWI pins ..................................................................................................................19 8.4GPIO pins ................................................................................................................19
9
Memories ................................................................................................ 20
9.1Embedded Memories ..............................................................................................20 9.2Physical Memory Map .............................................................................................20 9.3Bus Matrix Connections ..........................................................................................21
10 Peripherals ............................................................................................. 23
10.1Peripheral address map ........................................................................................23 10.2CPU Local Bus Mapping .......................................................................................24 10.3Interrupt Request Signal Map ................................................................................26 10.4Clock Connections ................................................................................................28 10.5Nexus OCD AUX port connections .......................................................................29 10.6PDC handshake signals ........................................................................................29 10.7Peripheral Multiplexing on I/O lines .......................................................................30 10.8Oscillator Pinout ....................................................................................................33 10.9USART Configuration ............................................................................................33 10.10GPIO ...................................................................................................................34
I
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10.11Peripheral overview .............................................................................................34
11 Boot Sequence ....................................................................................... 38
11.1Starting of clocks ...................................................................................................38 11.2Fetching of initial instructions ................................................................................38
12 Electrical Characteristics ...................................................................... 39
12.1Absolute Maximum Ratings* .................................................................................39 12.2DC Characteristics ................................................................................................40 12.3Regulator characteristics .......................................................................................41 12.4Analog characteristics ...........................................................................................41 12.5Power Consumption ..............................................................................................42 12.6Clock Characteristics .............................................................................................44 12.7Crystal Oscillator Characteristis ............................................................................44 12.8ADC Characteristics ..............................................................................................46 12.9EBI Timings ...........................................................................................................47 12.10JTAG Timings ......................................................................................................53 12.11SPI Characteristics ..............................................................................................54 12.12MACB Characteristics .........................................................................................56 12.13Flash Characteristics ...........................................................................................58
13 Mechanical Characteristics ................................................................... 59
13.1Thermal Considerations ........................................................................................59 13.2Package Drawings ................................................................................................60 13.3Soldering Profile ....................................................................................................62
14 Ordering Information ............................................................................. 63
14.1Automotive Quality Grade .....................................................................................63
15 Errata ....................................................................................................... 64
15.1Rev. J ....................................................................................................................64 15.2Rev. I .....................................................................................................................67 15.3Rev. H ...................................................................................................................70 15.4Rev. E ....................................................................................................................73
16 Datasheet Revision History .................................................................. 82
16.1Rev. F - 08/08 .......................................................................................................82 16.2Rev. E - 04/08 .......................................................................................................82 16.3Rev. D - 04/08 ......................................................................................................82 16.4Rev. C - 10/07 ......................................................................................................82
16.5Rev. B - 10/07 .......................................................................................................82 16.6Rev. A - 03/07 .......................................................................................................83 Headquarters
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32058FS-AVR32-08/08

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